1. Field
Aspects discussed herein relate to an analog-to-digital converter device.
2. Description of Related Art
A successive approximation routine (SAR) analog-to-digital converter (ADC) compares a voltage of an analog input signal with an output voltage of a digital-to-analog (DA) converter through a comparator, and determines a digital signal to be supplied to the DA converter in response to comparison results in the order of upper to lower bits. The SAR-ADC calculates an approximate digital value in voltage. The operation speed of the SAR-ADC may be determined by an output operation time of the DA converter.
Related art is discussed in Japanese Laid-Open Patent Publication No. H1-185025, Japanese Laid-Open Patent Publication No. 2005-45795, and Japanese Laid-Open Patent Publication No. 2009-118488.